Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. This saves power by adding more logic to a circuit to the clock by disabling clock switching, so that the flip-flops in them do not have to switch states. As a result, the switching power consumption goes to zero, and only leakage currents are incurred.
Clock gating logic can be added into a design in a variety of ways:
- Coded into the RTL
code as enable conditions that can be automatically translated into
clock gating logic by synthesis tools.
- Inserted into the design manually by the RTL designers (typically as
module level clock gating) by instantiating library specific ICG
(Integrated Clock Gating) cells to gate the clocks of specific modules
or registers.
- Semi-automatically inserted into the RTL by automated clock gating tools. These tools either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically also offer sequential clock gating optimisations.
Poor clock gating produces glitches in the output clock, making unwanted clock transitions which may lead to timing violations,etc., and increased power consumption.
Here is an Verilog example illustrating the RTL code for clock gating & its issues.
The below code produces simple clock gating mechanism with an 2-input AND gate, with inputs as CLK & CLK_EN. But the greatest disadvantage is that it produces glitches in output as in the below waveform.
//BAD clock gating, can cause glitches in output
assign clk_out1 = c_en && clk;
To overcome the glitches, a latching needs to be added to change the enable only when CLK is high/low. By this way, glitches are avoided & produces a good clock for the rest of the block.
//GOOD clock gating & glitch free
always @ (c_en or clk) begin
if (!clk)
en_out2 = c_en; // build latch
end
assign clk_out2 = en_out2 && clk;
Circuit synthesized for the above codes:
 |
| Verilog RTL - Clock gating- circuit :: ELecDude |
Waveform for the above code:
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